代码搜索：Comp
找到约 10,000 项符合「Comp」的源代码
代码结果 10,000
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vhd 4_comp.vhd
entity bit_rtl_lt_nc is
port (
in1 : bit_vector;
in2 : bit_vector;
pout : out bit
);
end bit_rtl_lt_nc;
architecture func of bit_rtl_lt_nc is
begin
process(in1,in2)
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vhd 33_comp.vhd
--**VHDL*************************************************************
--
-- SRC-MODULE : COMP
-- NAME : comp.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Architecture of COMP benchmark
--
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xco buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
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xcp buffer_comp.xcp
# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enab
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vhd buffer_comp.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
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edn buffer_comp.edn
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 10 9 1 3 47)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xil
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vho buffer_comp.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
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asm comp_corr.asm
*****************************************************************************
** Description: comp_corr() in calc_cor.c **
**
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m comp_rev.m
% Asymmetry due to time reversal, as described in Schreiber and Schmitz (1997).
%
% Usage: r = temu_rev (X, tau);
function r = temu_rev (Xo, tau)
if (nargin
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