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Clock 的代码
clock_divider.v
//---------------------------------------------------------------------------
// Clock divider core
//
//
// Description: See description below (which suffices for IP core
//
clock_multiply.v
//-----------------------------------------------------------------------------
//
// Author: John Clayton
// Update: June 5, 2001 Typed this file in from the Xilinx file "rec019.html"
//
// De
rel_clock.qpf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
rel_clock.done
Mon May 26 18:53:17 2008
rel_clock.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
rel_clock.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
rel_clock.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[P
rel_clock.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
rel_clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuzizhong is
port(clk,set,change,s1,s2,s3:in std_logic;
second1,second2,minite1,minite2,hour1,hour2:o