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Clock 的代码
clock_div.v
module clock_div(oclk,iclk);
output reg oclk;
input iclk;
reg [19:0]counter1 = 0;
always@(posedge iclk )
begin
if(counter1
clock_div.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
clock_div.done
Wed Jun 04 21:05:56 2008
clock_div.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
clock_div.hif
Version 7.1 Build 156 04/30/2007 SJ Full Version
11
912
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
clock_div.qpf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu