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# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

-- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock_6 is port(clk:in std_logic; --时钟输入20MHz clr:in std_logic; --清零端 en:in std_logic; --暂停信号 m

Sun May 18 10:03:12 2008

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 [P

Version 7.2 Build 151 09/26/2007 SJ Full Version 38 2275 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Path

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| c8e471035a36d2392e9b764c2517578 clock_6:inst 6b9322a3ed954cf3ac41c97fa1f8d9 altpll0:inst2 163982d2f8fc822b40372848cce1b617 altpll0:inst2|altpll:altpll_component d4b92ea4fba4c49118598123ca13cf