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Clock 的代码
clock.jid
. clock clock.v f:\实验\xilinx\clock\clock.v
clock.xst
set -tmpdir .
set -overwrite YES
run
-ifmt VERILOG
-top clock
-p XC9500
-ifn clock.prj
-opt_mode Speed
-opt_level 1
-check_attribute_syntax YES
-keep_hierarchy YES
-fsm_extract YES -fsm_enc
clock._prj
insert `timescale 1ns/1ns
include
include clock.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
clock.prj
`timescale 1ns/1ns
`include "clock.v"
`include "d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v"
clock.npl
JDF E
// Created by ISE ver 1.0
PROJECT clock
DESIGN clock Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE clock.v
MODSTYLE clock Normal
[STRATEGY-LIST]
Normal=True, 10376
clock.jhd
MODULE clock
clock.ptf
[clock]
Generate Programming File=true
Design Entry Utilities=false
User Constraints=true
clock.h
/**
* \defgroup clock Clock interface
*
* The clock interface is the interface between the \ref timer "timer library"
* and the platform specific clock functionality. The clock
* interface must b
clock.__i
"clock.c" BROWSE DEBUG OBJECTEXTEND
clock.lst
C51 COMPILER V6.12 CLOCK 07/30/2008 14:29:23 PAGE 1
C51 COMPILER V6.12, COMPILATION OF MODULE CLOCK
OBJECT MODULE PLACED IN c