代码搜索结果
找到约 10,000 项符合
Clock 的代码
clock_my.fld
E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db
CLOCK_MY
yang
V1
clock_my.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
clock_my.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLOCK_MY IS
PORT( CLK : IN STD_LOGIC; --CPLD系统时钟
SENSOR_A : IN STD_LOGIC;
clock_divider.v
// hds_header_start
//
// Module UART_TXT.clock_divider.rtl
//
// Created:
// by - user.group (host.domain)
// at - 19:13:31 28 Aug 2001
//
// Generated by Mentor Graphics' H