代码搜索:Clock

找到约 10,000 项符合「Clock」的源代码

代码结果 10,000
www.eeworm.com/read/265643/11259205

ngd clock.ngd

www.eeworm.com/read/265643/11259208

pnx clock.pnx

www.eeworm.com/read/265643/11259210

bld clock.bld

Release 4.1WP3.x - ngdbuild E.33 Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc clock.ucf -p XC9500 clock.ngc clock.ngd Reading NGO file "F:/ /Xil
www.eeworm.com/read/265643/11259223

mfd clock.mfd

MDF Database: version 1.0 MDF_INFO | clock | XC95108-7-PC84 MACROCELL | 4 | 13 | N612 ATTRIBUTES | 396034 | 0 INPUTS | 17 | count_10 | count_11 | min_6.FBK.LFBK | min_7.FBK.LFBK | min_3.FBK.L
www.eeworm.com/read/265643/11259224

prj clock.prj

`timescale 1ns/1ns `include "clock.v" `include "d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/265643/11259225

npl clock.npl

JDF E // Created by ISE ver 1.0 PROJECT clock DESIGN clock Normal DEVKIT XC95108 PC84 DEVFAM xc9500 FLOW XST Verilog MODULE clock.v MODSTYLE clock Normal [STRATEGY-LIST] Normal=True, 10376
www.eeworm.com/read/265643/11259227

jhd clock.jhd

MODULE clock
www.eeworm.com/read/265643/11259231

syr clock.syr

Release 4.1WP3.x - xst E.33 Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to . CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YES
www.eeworm.com/read/265643/11259240

ngc clock.ngc

www.eeworm.com/read/265643/11259243

ucf clock.ucf

// Template UCF file created by the Project Navigator NET clk LOC=P9; NET lddat LOC=P40; NET lddat LOC=P41; NET lddat LOC=P43; NET lddat LOC=P44; NET lddat LOC=P45; NET lddat L