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Clock 的代码
clock.uv2
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (Target 1), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,1, 0x0
Options 1,0,0 // Targ
clock.odl
// Clock.odl : type library source for ActiveX Control project.
// This file will be processed by the Make Type Library (mktyplib) tool to
// produce the type library (Clock.tlb) that will become
clock.plg
Build Log
--------------------Configuration: Clock - Win32 Release--------------------
Command Lines
Creating command line "midl.exe /nologo /D
clock.dsp
# Microsoft Developer Studio Project File - Name="Clock" - Package Owner=
# Microsoft Developer Studio Generated Build File, Format Version 6.00
# ** DO NOT EDIT **
# TARGTYPE "Win32 (x86) Dyn
clock.h
/*H**************************************************************************
* NAME: clock.h
*----------------------------------------------------------------------------
* Copyright (c) 2
clock.odl
// Clock.odl : type library source for ActiveX Control project.
// This file will be processed by the Make Type Library (mktyplib) tool to
// produce the type library (Clock.tlb) that will become
clock.jid
. clock clock.v f:\dp-fpga\实验例程\clock\clock.v
clock.xst
set -tmpdir .
set -overwrite YES
run
-ifmt VERILOG
-top clock
-p xc2s100-pq208-5
-ifn clock.prj
-opt_mode Speed
-opt_level 1
-check_attribute_syntax YES
-keep_hierarchy No
-glob_opt AllCloc
clock._prj
insert `timescale 1ns/1ns
include
include clock.v
include d:/xilinx_webpack/verilog/src/iSE/unisim_comp.v
clock.prj
`timescale 1ns/1ns
`include "clock.v"
`include "d:/xilinx_webpack/verilog/src/iSE/unisim_comp.v"