代码搜索：Clock
找到约 10,000 项符合「Clock」的源代码
代码结果 10,000
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pof clock.pof
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vhd clock.vhd
-----------the clock top design file
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clock is
port(clk_20m : in std_logic;----2
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pin clock.pin
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
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cdf clock.cdf
/* Quartus II Version 4.0 Build 190 1/28/2004 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPF10K10L84) Path("F:/yys_eda_code/clo
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hif clock.hif
Version 5.1 Build 176 10/26/2005 SJ Full Version
17
882
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
reg
# storage
db|
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psp clock.psp
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dbp clock.dbp
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qpf clock.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth