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dot_model_ref.deck
Model card reference
*
* This circuit contains simple gain blocks that share a
* single .model card.
*
.tran 1e-5 1e-3
*
v1 1 0 0.0 sin(0 1 1k)
r1 1 0 1k
*
a1 1 2 gain_block
r2 2 0 1k
*
a2 1 3 gain_bl
param_defaults.deck
Parameter defaults
*
* This circuit contains a code model with
* parameters of various types, which are all defaulted,
* and prints the default values.
*
.op
*
r1 1 0 1k
r2 2 0 1k
r3 1 2 1k
nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
*/
#include
#include "global.h"
#include "mbuf.h"
#include "timer.h"
#include "ax25.h"
#include "netrom.h"
#include "n
nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
*/
#include
#include "global.h"
#include "mbuf.h"
#include "timer.h"
#include "ax25.h"
#include "netrom.h"
#include "n
chp8ex2.m
fprintf('\n Wait simulation is in process. \n')
VF = 400; rF = 0.4; iF0 = VF/rF;
f = 60; w=2.*pi*f;
d = 0; d=d*pi/180;
t0 = 0 ; tfinal = 0.80;
i0 = [0; iF0; 0; 0; 0 ]; % Initial current
nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
*/
#include
#include "global.h"
#include "mbuf.h"
#include "timer.h"
#include "ax25.h"
#include "netrom.h"
#include "n
chp8ex2.m
fprintf('\n Wait simulation is in process. \n')
VF = 400; rF = 0.4; iF0 = VF/rF;
f = 60; w=2.*pi*f;
d = 0; d=d*pi/180;
t0 = 0 ; tfinal = 0.80;
i0 = [0; iF0; 0; 0; 0 ]; % Initial current