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nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
*/
#include
#include "global.h"
#include "mbuf.h"
#include "timer.h"
#include "ax25.h"
#include "netrom.h"
#include "n
新建 文本文档.txt
: koko (koko), 信区: Circuit
标 题: Re: 请教7805，7905，7812，7912的管脚排列？？
发信站: BBS 水木清华站 (Sat Apr 27 10:21:49 2002)
78X和79X的引脚排列是这样的：
1脚电压比2脚高就行了。
因此，78X的1脚是输入，2脚为地，3脚输出。因为78X为正电压。
79X的1脚
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
*/
#include
#include "global.h"
#include "mbuf.h"
#include "timer.h"
#include "ax25.h"
#include "netrom.h"
#include "n
readme
This directory contains the CIDER serial-version benchmarks used in the
thesis "Design-Oriented Mixed-Level Circuit and Device Simulation" by
David A. Gates.
test11.cir
*** For BSIM3V3 general purpose check (Id-Vg) for Pmosfet***
******************************************
*** circuit description ***
m1 2 1 0 3 p1 L=0.35u W=10.0u
vgs 1 0 -3.5
vds 2 0 -0.1
vbs 3 0 0
test11.cir
*** For BSIM3V3 general purpose check (Id-Vg) for Pmosfet***
******************************************
*** circuit description ***
m1 2 1 0 3 p1 L=0.35u W=10.0u
vgs 1 0 -3.5
vds 2 0 -0.1
vbs 3 0 0