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c6ex2.m
% MATLAB symbolic toolbox solution for voltage vL2 in
% Example 5-2 after open circuit occurs
%
VL2 = sym('5*s*30*(s+1/3)/(s*(s+1/2))-200');
VL2_P = diff(int(VL2))
vL2 = ilaplace(VL2)
dagon.h
#include
#include
#define INV 0
#define NAND 1
#define RIGHT 0
#define LEFT 1
/* define structure type */
struct lib;
typedef struct gate {
char type ; /*
nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
* Copyright 1989 by Daniel M. Frank, W9NK. Permission granted for
* non-commercial distribution only.
*/
#include
#inc
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
nr4.h
#ifndef _NR4_H
#define _NR4_H
/* nr4.h: defines for netrom layer 4 (transport) support */
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#ifndef _A
nr4subr.c
/*
* nr4subr.c: subroutines for net/rom transport layer.
*/
#include
#include "global.h"
#include "mbuf.h"
#include "timer.h"
#include "ax25.h"
#include "netrom.h"
#include "n
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块