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Protel Design System Design Rule Check PCB File : \U\完成稿\例子\PCI接口电路\PCI接口电路.PcbDoc Date : 2005-3-16 Time : 14:09:08 Processing Rule : Width Constraint (Min=8mil) (Max=100mil) (Preferred=

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Starting EDIF2BLIF.... EDIF2BLIF: Warning: Net GND is floating and will be removed. EDIF2BLIF: Warning: Net VCC is floating and will be removed. readEDIF ended normally. Inspect circuit COUN

The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS Copyright

*** For BSIM3V3 general purpose check (Id-Vd) for Pmosfet *** ****************************************** *** circuit description *** m1 2 1 0 0 p1 L=0.35u W=10.0u vgs 1 0 -3.5 vds 2 0 -3.5 .dc vds

*** For BSIM3V3 general purpose check (Id-Vg) for Nmosfet*** ****************************************** *** circuit description *** m1 2 1 0 3 n1 L=0.35u W=10.0u vgs 1 0 3.5 vbs 3 0 0 vds 2 0 0.

*** For BSIM3V3 general purpose check (Id-Vg) for Pmosfet*** ****************************************** *** circuit description *** m1 2 1 0 3 p1 L=0.35u W=10.0u vgs 1 0 -3.5 vds 2 0 -0.1 vbs 3 0 0

*** For BSIM3V3 general purpose check (Id-Vg) for Nmosfet*** ****************************************** *** circuit description *** m1 2 1 0 3 n1 L=0.35u W=10.0u vgs 1 0 3.5 vbs 3 0 0 vds 2 0 0.

*****Single NMOS Transistor For BSIM3V3 general purpose check (Id-Vd) *** *** circuit description *** m1 2 1 0 0 n1 L=0.35u W=10.0u vgs 1 0 3.5 vds 2 0 3.5 .dc vds 0 3.5 0.05 vgs 0 3.5 0.5 .opt

*** For BSIM3V3 general purpose check (Id-Vg) for Nmosfet*** ****************************************** *** circuit description *** m1 2 1 0 3 n1 L=0.35u W=10.0u vgs 1 0 3.5 vbs 3 0 0 vds 2 0 0.