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Model card reference * * This circuit contains simple gain blocks that share a * single .model card. * .tran 1e-5 1e-3 * v1 1 0 0.0 sin(0 1 1k) r1 1 0 1k * a1 1 2 gain_block r2 2 0 1k * a2 1 3 gain_bl

* Figure 33.1 CMOS: Mixed-Signal Circuit Design * *** Top Level Netlist *** M1 3 4 0 0 NMOSL1 L=0.5u W=3u M2 5 4 0 0 NMOSEKV L=0.5u W=3u Vds 2 0 DC 0 Vgs 4 0 DC 0 VIMTR1 2 3 0V VIMTR2 2 5 0

* Figure 33.53 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb pmos W=20 L=1 M2 Vd2 Vg Vs Vb pmos W=40 L=2 M3 Vd3 Vg Vs Vb pmos W=60 L=3 M4 Vd4 Vg Vs Vb pmos W=80 L=4 Vg Vg 0 DC 1.0 V

* Figure 33.52 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb nmos W=10 L=1 M2 Vd2 Vg Vs Vb nmos W=20 L=2 M3 Vd3 Vg Vs Vb nmos W=30 L=3 M4 Vd4 Vg Vs Vb nmos W=40 L=4 Vg Vg 0 DC 0.5 Vs

// example of RLC circuit // L and R comes from wires dx 0.2e-6 time 1e-6 Nx 50 Ny 55 Nz 25 matlaboutput // x1 x2 y1 y2 z1 z2 sig r_eps box 10 40 10 14 10 14 1e6 1 box 10 40 40 44 10 14 1e6 1

********************** test circuit No. 3 ************************** c1g 1 0 1P l11a 1 1a 6e-9 r1a7 1a 7 0.025K rin6 in 6 0.075K l67 6 7 10e-9 c7g 7 0 1P P2 2 1 7 2 8 PLINE .MODEL PLINE CPL +R

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "共射—共基组合电路图" " 扩展频带三种方法：反馈、补偿、组合电路。" " 电路中第一级是共发组态电路；第二级是共基组态电路。" " 共基级的输入阻抗成为共射极的负载。由于共基级电路有很低

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: " 该图是用四个JK触发器构成的异步二进制减法计数电路。它和异步加法计数电路没有很大差别。只是第二级以后的时钟脉冲由前一级的Q`端接入，其它分析相同。" " 异步减法计数器状态转移表：" "

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: " 数据选择器也称多路选择器或多路开关，其基本逻辑功能是在选择信号控制下，从若干路输入数据中选择一路作为输出。该图为4选1数据选择器。当使能输入端ST`=0时，输出函数表达式为：" "

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "小电流恒流源电路图（又称为微电流镜）" " 令BG2发射极负载电阻为0，避免R1的取值过大以及在工艺上为了制作高欧姆电阻而占用芯片面积过大。这种电流镜称为微电流镜。" " 由： 经过电阻R的电流：Ir=Is