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Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "(1)由图可知：Av=Vout/Vs, Au=5.5 ,Vo(eff)=5.5V" "(2)Vo(eff)=5.5V，理论与测试值相符。" "(3)若要求Vo(eff)=10V则W1应为190K。" "（4）将T1改为LM324

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "(1)由图可知：Av=Vout/Vs, Au=5.5 ,Vo(eff)=5.5V" "(2)Vo(eff)=5.5V，理论与测试值相符。" "(3)若要求Vo(eff)=10V则W1应为190K。" "（4）将T1改为LM324

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "(1)由图可知：Av=Vout/Vs, Au=5.5 ,Vo(eff)=5.5V" "(2)Vo(eff)=5.5V，理论与测试值相符。" "(3)若要求Vo(eff)=10V则W1应为190K。" "（4）将T1改为LM324

% Electric circuit simulator in CLP(R) % resistor( T1, T2, R): % R=resistance; T1, T2 its terminals resistor( (V1,I1), (V2,I2), R) :- { I1 = -I2, V1-V2 = I1*R }. % diode( T1, T2): %

* Figure 33.57 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb pmos W=40 L=2 Vg Vg 0 DC 1.0 AC 1 Vs Vs 0 DC 1.5 Vb Vb 0 DC 1.5 Vd Vd 0 DC 1.4 Vd1 Vd1 Vd DC 0 .ac dec 100 100MEG 10

* Figure 33.55 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb pmos W=40 L=2 Vg Vg 0 DC 1.0 AC 1 Vs Vs 0 DC 1.5 Vb Vb 0 DC 1.5 Vd Vd 0 DC 1.4 Vd1 Vd Vd1 DC 0 .ac dec 100 1MEG 1G

* Figure 33.54 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb nmos W=20 L=2 Vg Vg 0 DC 0.5 AC 1 Vs Vs 0 DC 0 Vd Vd 0 DC 0.1 Vd1 Vd Vd1 DC 0 Vb 0 Vb DC 0 .ac dec 100 1MEG 1G .

* Figure 33.74 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vinp Vinp 0 DC 0.75 RF Vout Vinm 10k Ri Vin Vinm 10k Cl Vout 0 5pf Vin Vin 0 DC 0 pulse 0.5 1.0 10n 1n 1n 50n 100n .tran 1

* Figure 33.46 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vclk clk 0 DC 0 pulse 0 1.5 0 .1n .1n 4.9n 10n X1 Vout Vout clk vdd dtspc CL Vout 0 30f .tran .2n 40n 0n .2n .option s

STATIC LATCH *** IC=1MA, RE6=3K *** SPICE ORIGINAL 1-7-80, CIDER REVISED 4-16-93 *** BIAS CIRCUIT *** RESISTORS RCC2 6 8 3.33K REE2 9 0 200 *** TRANSISTORS Q1 6 8 4 M_NPN1D AREA=8 Q2 8 4 9