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MiXeD CaSe * * This circuit contains a simple gain block to demonstrate * that the simulator deck parsing code is case-insensitive. * .TrAn 1E-5 1e-3 * V1 1 0 0.0 sIn(0 1 1k) r1 1 0 1k * A1 1 2 GaIn_B

Parameter types * * This circuit contains a code model which accepts several * parameters of various types and prints them. * .op * r1 1 0 1k r2 2 0 1k r3 1 2 1k * a1 [1 2] mod .model mod print_param_

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "" "" EncryptionType: 2 UsingVectorGraphics: 0 /000@D0I0?4D

/board1.png/1.1.1.1/Fri Aug 3 21:51:45 2001// /board2.png/1.1.1.1/Fri Aug 3 21:52:08 2001// /board3.png/1.1.1.1/Fri Aug 3 21:52:31 2001// /circuit.txt/1.1.1.1/Fri Aug 3 21:52:32 2001// /commands.h

* Figure 33.21a CMOS: Mixed-Signal Circuit Design * M1 Vd Vg Vs Vb pmos W=20 L=1 Vg 0 Vg DC 0 Vs 0 Vs DC 0 Vd 0 Vd DC 1.5 Vb Vb 0 DC 0 .DC Vd 0 1.51 0.05 Vg 0.5 1.5 0.25 .options s

* Figure 33.20a CMOS: Mixed-Signal Circuit Design * M1 Vd Vg Vs Vb nmos W=10 L=1 Vg Vg 0 DC 0 Vs Vs 0 DC 0 Vd Vd 0 DC 1.5 Vb 0 Vb DC 0 .DC Vd 0 1.5 0.05 Vg 0.5 1.5 0.25 .options sc

* Figure 33.20b CMOS: Mixed-Signal Circuit Design * M1 Vd Vg Vs Vb nmos W=10 L=1 Vg Vg 0 DC 0 Vs Vs 0 DC 0 Vd Vd 0 DC 1.5 Vb 0 Vb DC 0 .DC Vg 0 1.5 0.05 Vb 0 1.25 0.25 .options scal

* Figure 33.21b CMOS: Mixed-Signal Circuit Design * M1 Vd Vg Vs Vb pmos W=20 L=1 Vg 0 Vg DC 0 Vs 0 Vs DC 0 Vd 0 Vd DC 1.5 Vb Vb 0 DC 0 .DC Vg 0 1.5 0.05 Vb 0 1.25 0.25 .options scal

* Figure 33.61 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vtest Vtest 0 DC 0 .DC Vtest 0 1.5 .01 temp 0 100 25 X1 Vbias1 Vbias2 Vbias3 Vbias4 Vbiasn Vbiasn2 Vbiasp Vbiasp2 Vhigh Vlow

** PMOSFET: Benchmarking Implementation of BSIM4.4.0 by Jane Xi 01/30/2004. ** Circuit Description ** m1 2 1 0 b p1 L=0.09u W=10.0u rgeoMod=1 vgs 1 0 -1.2 vds 2 0 0.0 vbs b 0 0.0 *.dc vds 0 -1.2 -0.