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* Figure 33.63 CMOS: Mixed-Signal Circuit Design * .option scale=0.15u post Vdd Vdd 0 DC 1.5 Vin Vin 0 DC 0 .dc Vin 0 1.5 .01 X1 Vin Vout Vdd inverter .subckt inverter Vin Vout Vdd M

* Figure 33.37 CMOS: Mixed-Signal Circuit Design * .option scale=0.15u post Vdd Vdd 0 DC 1.5 Vin Vin 0 DC 0 .dc Vin 0 1.5 .01 X1 Vin Vout Vdd inverter .subckt inverter Vin Vout Vdd M

IO types * * This circuit contains a mix of input output types including * voltages, currents, digital signals, and user defined * signals. * .tran 1e-6 1e-4 * v1 1 0 0.0 pulse(0 1 2e-5) r1

User defined nodes * * This circuit contains a mix of node types including * two 'real' type user-defined nodes and associated * node bridges. * .tran 1e-6 1e-4 * v1 1 0 0.0 pulse(0 1 2e-5)

Test for the external circuit (IN MKS UNITS) -nsp---nc---nc2p---dt[s]-----r0[m]-----r1[m]------epsilonr-- 0 100 5e7 1e-9 0.01 .15 1 -rhoback[C/m^3]---backj[Amp/m^

Circuit: corresponding to ckt in swec Warning -- Level not specified on line "vto=0.8 kp=48u gamma=0.30 phi=0.55 lambda=0.00 cgso=0 cgdo=0 cj=0 cjsw=0 tox=18000n ld=0.0u" Using level 1. Warning -- L

Circuit: corresponding to ckt in swec Warning -- Level not specified on line "vto=0.8 kp=48u gamma=0.30 phi=0.55 lambda=0.00 cgso=0 cgdo=0 cj=0 cjsw=0 tox=18000n ld=0.0u" Using level 1. Warning -- L

Circuit: corresponding to ckt in swec Warning -- Level not specified on line "vto=0.8 kp=48u gamma=0.30 phi=0.55 lambda=0.00 cgso=0 cgdo=0 cj=0 cjsw=0 tox=18000n ld=0.0u" Using level 1. Warning -- L

IO types * * This circuit contains a mix of input output types including * voltages, currents, digital signals, and user defined * signals. * .tran 1e-6 1e-4 * v1 1 0 0.0 pulse(0 1 2e-5) r1

User defined nodes * * This circuit contains a mix of node types including * two 'real' type user-defined nodes and associated * node bridges. * .tran 1e-6 1e-4 * v1 1 0 0.0 pulse(0 1 2e-5)