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找到约 5,955 项符合 Circuit 的代码

parsing.deck

Parsing * * This circuit contains a simple gain block to demonstrate * that the simulator parses the syntax used to reference * code models. * .tran 1e-5 1e-3 * v1 1 0 0.0 sin(0 1 1k) r1 1 0

crosscompile.mpb

// -*- MPC -*- // crosscompile.mpb,v 1.2 2003/12/30 15:18:22 dhinton Exp project { verbatim(gnuace, circuit) { ifneq ($(CROSS-COMPILE),) all clean realclean idl_stubs: " @ech

ecn_vc.grn

.(z .hl .GS C width 6.0 high 4.0 1 8 2 10 3 12 4 14 sc 0.5 narrow 1 medium 3 thick 7 pointscale off file ecn_vc.gsrc .GE .ce \fBFigure \n+(FG:\fR Virtual Circuit State Diagram .)z

circuit1.clp

;;;====================================================== ;;; Example Circuit #1 ;;; ;;; An example circuit to be loaded for use with ;;; the "electronic.clp" example program. Note ;;;

circuit2.clp

;;;====================================================== ;;; Example Circuit #2 ;;; ;;; An example circuit to be loaded for use with ;;; the "electronic.clp" example program. This ;;;

circuit1.clp

;;;====================================================== ;;; Example Circuit #1 ;;; ;;; An example circuit to be loaded for use with ;;; the "electronic.clp" example program. Note ;;;

circuit2.clp

;;;====================================================== ;;; Example Circuit #2 ;;; ;;; An example circuit to be loaded for use with ;;; the "electronic.clp" example program. This ;;;

c6ex2.m

% MATLAB symbolic toolbox solution for voltage vL2 in % Example 5-2 after open circuit occurs % VL2 = sym('5*s*30*(s+1/3)/(s*(s+1/2))-200'); VL2_P = diff(int(VL2)) vL2 = ilaplace(VL2)

layout sp with level3.sp

CIRCUIT example * * IC Technology: CMOS 0.12祄 - 6 Metal * .op .dc iref .1u 220u .1u VDD 1 0 DC 1.20 ibias 1 7 DC 200u iref 1 6 DC 200u vo 2 0 DC .3 * * List of nodes * "N2" corresponds to

sumarize11_3_4.m

subplot(1,2,1) imshow circuit.tif I = imcrop; subplot(1,2,2) imshow(I);