代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/410728/2203074
cgs subxi.cgs
# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global subxi
subxi:
set_gr_immed 2,gr8
set_icc 0x0e,0 ; Make sure carry is off
subxi
www.eeworm.com/read/165173/10073417
vhd cnt4000.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY cnt4000 IS
PORT(reset,en,clk:IN STD_ULOGIC;
carry1:OUT STD_ULOGIC;
q:OUT STD_LOGIC_VECTOR(11 DOWNTO 0))
www.eeworm.com/read/165173/10073473
vhd cnt1000.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY cnt1000 IS
PORT(reset,en,clk:IN STD_ULOGIC;
carry1:OUT STD_ULOGIC;
q:OUT STD_ULOGIC_VECTOR(9 DOWNTO 0))
www.eeworm.com/read/165173/10073517
vhd cnt40000.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY cnt40000 IS
PORT(reset,en,clk:IN STD_ULOGIC;
carry1:OUT STD_ULOGIC;
q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
www.eeworm.com/read/165173/10073732
vhd cnt10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY cnt10 IS
PORT(reset,en,clk:IN STD_ULOGIC;
carry1:OUT STD_ULOGIC;
q:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0));
www.eeworm.com/read/162169/10329924
h diskinfo.h
#define VWIN32_DIOC_DOS_INT21 (1)
#define VWIN32_DIOC_DOS_INT25 (2)
#define VWIN32_DIOC_DOS_INT26 (3)
#define VWIN32_DIOC_DOS_DRIVEINFO (6)
#define CARRY_FLAG 1
#define READSEC
www.eeworm.com/read/464013/7170842
vhd fen24.vhd
-------------------------------------------------
--实体名：fen24
--功 能：24进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
--作 者：Haibing Li
--日 期：
www.eeworm.com/read/442382/7653758
h half_adder.h
// half_adder.h
#include "systemc.h"
SC_MODULE(half_adder){
sc_in a, b;
sc_out sum, carry;
void prc_half_adder();
SC_CTOR(half_adder){
SC_METHOD(prc_half_adder)
www.eeworm.com/read/240152/13235008
vhd counter1.1.vhd
--
-- Counter.vhd, contains 1) run-once down-counter 2) general purpose up-down riple-carry counter
--
-- Author: Richard Herveille
-- Rev. 1.0 march 7th, 2001
-- rev. 1.1 april 17th, 2001. Changed r
www.eeworm.com/read/137919/13279440
vhd counter10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(clr,en,clk:in std_logic;
carry0:out std_logic;
q:out std_logic_vector(3 downto 0));