代码搜索：Cache
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www.eeworm.com/read/288937/3998954
h cache.h
/*
* linux/include/asm-arm/proc-armv/cache.h
*
* Copyright (C) 1999-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU G
www.eeworm.com/read/288937/3998973
h cache.h
/*
* linux/include/asm-arm/proc-armo/cache.h
*
* Copyright (C) 1999-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU G
www.eeworm.com/read/288937/3998993
h cache.h
/*
* linux/include/asm-arm/cache.h
*/
#ifndef __ASMARM_CACHE_H
#define __ASMARM_CACHE_H
#define L1_CACHE_BYTES 32
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACH
www.eeworm.com/read/288894/4001836
java cache.java
//$Id: Cache.java 6478 2005-04-21 07:57:19Z oneovthafew $
package org.hibernate.cache;
import java.util.Map;
/**
* Implementors define a caching algorithm. All implementors
* must be
www.eeworm.com/read/288816/4004381
c cache.c
#include "instr.h"
#include "emul.h"
int
decode_cache(MIPS_State* mstate, Instr instr) //Use in Cache Instruction, it's unuseable in R3000
{
// CP0 is usable in kernel mode or when the CU bit i
www.eeworm.com/read/288816/4004383
h cache.h
#ifndef _CACHE_H_
#define _CACHE_H_
#include "types.h"
/* This header describes a physically-indexed, physically-taged MIPS cache.
* Both direct mapped and n-way set-associative caches are supporte
www.eeworm.com/read/288816/4004411
c cache.c
#include "armdefs.h"
/* mmu cache init
*
* @cache_t :cache_t to init
* @width :cache line width in byte
* @way :way of each cache set
* @set :cache set num
*
* $ -1: error
* 0: sucess
*/
www.eeworm.com/read/288816/4004412
h cache.h
#ifndef _MMU_CACHE_H_
#define _MMU_CACHE_H_
typedef struct cache_line_t
{
ARMword tag; /* cache line align address |
bit2: last half dirty
bit1: first half dirty
bit0: cac