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h cache.h

/* * include/asm-i386/cache.h */ #ifndef __ARCH_I386_CACHE_H #define __ARCH_I386_CACHE_H #include /* L1 cache line size */ #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) #defi
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h cache.h

#ifndef _ASM_CACHE_H #define _ASM_CACHE_H /* Etrax 100LX have 32-byte cache-lines. When we add support for future chips * here should be a check for CPU type. */ #define L1_CACHE_BYTES 32 #endif
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h cache.h

/* * include/asm-m68k/cache.h */ #ifndef __ARCH_M68K_CACHE_H #define __ARCH_M68K_CACHE_H /* bytes per L1 cache line */ #define L1_CACHE_BYTES 16 #endif
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h cache.h

/* * include/asm-s390/cache.h * * S390 version * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation * * Derived from "include/asm-i386/cache.h" * Copyright (C) 1992,
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h cache.h

/* * linux/include/asm-arm/proc-armv/cache.h * * Copyright (C) 1999-2001 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU G
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h cache.h

/* * linux/include/asm-arm/proc-armo/cache.h * * Copyright (C) 1999-2001 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU G
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h cache.h

/* * linux/include/asm-arm/cache.h */ #ifndef __ASMARM_CACHE_H #define __ASMARM_CACHE_H #define L1_CACHE_BYTES 32 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACH
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h cache.h

/* * include/asm-alpha/cache.h */ #ifndef __ARCH_ALPHA_CACHE_H #define __ARCH_ALPHA_CACHE_H #include /* Bytes per L1 (data) cache line. */ #if defined(CONFIG_ALPHA_GENERIC) || def
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h cache.h

/* * include/asm-parisc/cache.h */ #ifndef __ARCH_PARISC_CACHE_H #define __ARCH_PARISC_CACHE_H /* ** XXX FIXME : L1_CACHE_BYTES (cacheline size) should be a boot time thing. ** ** 32-bit on PA2.0
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h cache.h

/* $Id: cache.h,v 1.3 2000/07/04 06:24:49 gniibe Exp $ * * include/asm-sh/cache.h * * Copyright 1999 (C) Niibe Yutaka */ #ifndef __ASM_SH_CACHE_H #define __ASM_SH_CACHE_H /* bytes per L1 cache l
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