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s cache.s

/* * File: arch/blackfin/mach-common/cache.S * Based on: * Author: LG Soft India * * Created: * Description: cache control support * * Modified: * Copyright 2004-
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c cache.c

#include #include #include #include /* This file is used to workaround a cache bug, Guinness TR 106. */ inline void flush_dma_d
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c cache.c

/* * linux/arch/m32r/mm/cache.c * * Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara */ #include #undef MCCR #if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32
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c cache.c

/* * Copyright (c) 2004 Topspin Communications. All rights reserved. * Copyright (c) 2005 Intel Corporation. All rights reserved. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
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h cache.h

/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $ * cache.h: Cache specific code for the Sparc. These include flushing * and direct tag/data line access. * * Copyright (C) 1995 Dav
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h cache.h

#ifndef _ARCH_X86_CACHE_H #define _ARCH_X86_CACHE_H /* L1 cache line size */ #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1
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h cache.h

/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997
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h cache.h

#ifndef __ASM_AVR32_CACHE_H #define __ASM_AVR32_CACHE_H #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1
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h cache.h

/* * include/asm-sparc64/cache.h */ #ifndef __ARCH_SPARC64_CACHE_H #define __ARCH_SPARC64_CACHE_H /* bytes per L1 cache line */ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES 32 /* T
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h cache.h

#ifndef __LINUX_CACHE_H #define __LINUX_CACHE_H #include #include #ifndef L1_CACHE_ALIGN #define L1_CACHE_ALIGN(x) ALIGN(x, L1_CACHE_BYTES) #endif #ifndef SMP_CACHE_B
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