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s cache.s

#define ASSEMBLY #include #include .text .align 2 ENTRY(blackfin_icache_flush_range) R2 = -32; R2 = R0 & R2; P0 = R2; P1 = R1; CSYNC; 1: IFLUSH[P0++
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c cache.c

/* * Copyright (C) 2004-2006 Atmel Corporation * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * mod
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s cache.s

#include #include #include #include #include #include #include #ifndef CACHE_LINE_SIZE # define CACHE_LINE_
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cache config.cache

# This file is a shell script that caches the results of configure # tests run on this system so they can be shared between configure # scripts and configure runs. It is not useful on other systems
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cache config.cache

# This file is a shell script that caches the results of configure # tests run on this system so they can be shared between configure # scripts and configure runs. It is not useful on other systems
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www.eeworm.com/read/196926/5100034

c cache.c

#include "instr.h" #include "emul.h" int decode_cache(MIPS_State* mstate, Instr instr) //Use in Cache Instruction, it's unuseable in R3000 { // CP0 is usable in kernel mode or when the CU bit i
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h cache.h

#ifndef _CACHE_H_ #define _CACHE_H_ #include "types.h" /* This header describes a physically-indexed, physically-taged MIPS cache. * Both direct mapped and n-way set-associative caches are supporte
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c cache.c

#include "armdefs.h" /* mmu cache init * * @cache_t :cache_t to init * @width :cache line width in byte * @way :way of each cache set * @set :cache set num * * $ -1: error * 0: sucess */
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h cache.h

#ifndef _MMU_CACHE_H_ #define _MMU_CACHE_H_ typedef struct cache_line_t { ARMword tag; /* cache line align address | bit2: last half dirty bit1: first half dirty bit0: cac
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www.eeworm.com/read/196550/5101730

c cache.c

//koodailar add for mingw 2005.12.18 ---------------------------------------- #ifdef __MINGW32__ #include "arch/arm/common/armdefs.h" #else #include "armdefs.h" #endif // end -------------------------
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