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www.eeworm.com/read/209559/4970071

h cache.h

/* * include/asm-i386/cache.h */ #ifndef __ARCH_I386_CACHE_H #define __ARCH_I386_CACHE_H #include /* L1 cache line size */ #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) #defi
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h cache.h

#ifndef _ASM_CACHE_H #define _ASM_CACHE_H #include #endif /* _ASM_CACHE_H */
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h cache.h

#ifndef _ASM_ARCH_CACHE_H #define _ASM_ARCH_CACHE_H /* Etrax 100LX have 32-byte cache-lines. */ #define L1_CACHE_BYTES 32 #define L1_CACHE_SHIFT 5 #define L1_CACHE_SHIFT_MAX 5 #endif /* _ASM_ARCH_CA
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h cache.h

/* * include/asm-m68k/cache.h */ #ifndef __ARCH_M68K_CACHE_H #define __ARCH_M68K_CACHE_H /* bytes per L1 cache line */ #define L1_CACHE_SHIFT 4 #define L1_CACHE_BYTES (1
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h cache.h

/* * include/asm-v850/cache.h -- Cache operations * * Copyright (C) 2001 NEC Corporation * Copyright (C) 2001 Miles Bader * * This file is subject to the terms and conditions
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h cache.h

/* * include/asm-s390/cache.h * * S390 version * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation * * Derived from "include/asm-i386/cache.h" * Copyright (C) 1992,
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h cache.h

/* * linux/include/asm-arm/cache.h */ #ifndef __ASMARM_CACHE_H #define __ASMARM_CACHE_H #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1
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h cache.h

/* * include/asm-alpha/cache.h */ #ifndef __ARCH_ALPHA_CACHE_H #define __ARCH_ALPHA_CACHE_H #include /* Bytes per L1 (data) cache line. */ #if defined(CONFIG_ALPHA_GENERIC) || def
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h cache.h

/* * include/asm-parisc/cache.h */ #ifndef __ARCH_PARISC_CACHE_H #define __ARCH_PARISC_CACHE_H #include /* * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have *
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h cache.h

#ifndef __ARCH_H8300_CACHE_H #define __ARCH_H8300_CACHE_H /* bytes per L1 cache line */ #define L1_CACHE_BYTES 4 /* m68k-elf-gcc 2.95.2 doesn't like these */ #define __cacheline_aligned #d
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