代码搜索：CS3
找到约 88 项符合「CS3」的源代码
代码结果 88
www.eeworm.com/read/14659/401132
v decode_cmb.v
module decode_cmb (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
reg cs1, cs
www.eeworm.com/read/14659/401146
v decode_cmb2.v
module decode_cmb2 (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
wire cs1,
www.eeworm.com/read/14659/401151
v decode_cmb.v
module decode_cmb (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
reg cs1, cs
www.eeworm.com/read/14659/401263
v if_single_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg
www.eeworm.com/read/14659/401326
v if_mult_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_mult_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [
www.eeworm.com/read/14659/401405
v case_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module case_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [3
www.eeworm.com/read/269205/4246796
v if_single_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg
www.eeworm.com/read/269205/4246833
v if_mult_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_mult_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [
www.eeworm.com/read/269205/4246877
v case_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module case_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [3
www.eeworm.com/read/429003/1952318
v if_single_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg