代码搜索：CS2
找到约 499 项符合「CS2」的源代码
代码结果 499
www.eeworm.com/read/14659/401151
v decode_cmb.v
module decode_cmb (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
reg cs1, cs
www.eeworm.com/read/167675/9955955
v lcd.v
module lcd(clk,data,rst,rs,rw,en,cs1,cs2,test);
input clk,rst;
output [7:0] data;
output rs,rw,en,cs1,cs2;
output [3:0]test;
reg [3:0] test;
reg [7:0] data,xaddr,yaddr,xpage;
reg [7:0] rom1
www.eeworm.com/read/436479/7769343
v lcd.v
module lcd(clk,data,rst,rs,rw,en,cs1,cs2,test);
input clk,rst;
output [7:0] data;
output rs,rw,en,cs1,cs2;
output [3:0]test;
reg [3:0] test;
reg [7:0] data,xaddr,yaddr,xpage;
reg [7:0] rom1
www.eeworm.com/read/364315/9912519
asm qiangdaqi.asm
; 实验四:抢答器
; 08001214 钱程
; 08001214.ASM
; CS1 CS2 CS4 IRQ2 CLK0 CLK1 GATE0 GATE1
; CS1 CS2 CS-53 OUT1 Q0 OUT0 VCC VC
www.eeworm.com/read/399134/7887045
asm lcd.asm
//==========================================说明=============================================
// DI/RS:IOB3 R/W:IOB4 E:IOB5 CS1:IOB6 CS2:IOB7
// CS1和CS2只能有一个为低
//程序规范：每个函数写数据前自己清零数
www.eeworm.com/read/14659/401263
v if_single_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg
www.eeworm.com/read/14659/401326
v if_mult_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_mult_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [
www.eeworm.com/read/14659/401405
v case_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module case_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [3
www.eeworm.com/read/269205/4246796
v if_single_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg
www.eeworm.com/read/269205/4246833
v if_mult_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_mult_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [