代码搜索：CPU卡 开发教程
找到约 10,000 项符合「CPU卡 开发教程」的源代码
代码结果 10,000
www.eeworm.com/read/462150/7208566
o os_cpu_a.o
www.eeworm.com/read/462030/7212056
vhd board_cpu.vhd
--
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, c
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bit board_cpu.bit
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vhd cpu_pack.vhd
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_pack is
type cyc
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ucf board_cpu.ucf
NET "clk40" TNM_NET = "clk40";
TIMESPEC "TS_clk40" = PERIOD "clk40" 25 ns HIGH 50 %;
#######################################################################
#
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vhd cpu_engine.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
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npl cpu16.npl
JDF F
// Created by Project Navigator ver 1.0
PROJECT cpu16
DESIGN cpu16 Normal
DEVFAM virtexe
DEVFAMTIME 1064066933
DEVICE xcv100e
DEVICETIME 1064066933
DEVPKG pq240
DEVPKGTIME 1064066933
DEVSPEED -6
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vhd cpu_test.vhd
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for th
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ise cpu16.ise
www.eeworm.com/read/461980/7213431
h os_cpu.h
/*
*********************************************************************************************************
* uC/OS-II
*