代码搜索:CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/150132/12310389
er1 dk3200ee.er1
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
www.eeworm.com/read/336669/12426034
c mini51test.c
#include
#include
#include
#include
unsigned char xdata CPLD_WREG _at_ 0xffe4;
unsigned char xdata CPLD_RREG _at_ 0xffe5;
unsigned char xdata
www.eeworm.com/read/231272/14242210
er1 dk3200_1.er1
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
www.eeworm.com/read/127697/14339971
er1 iap3300.er1
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
www.eeworm.com/read/209902/15211961
txt at91.txt
setmem 0xFFC0000C,1,32 Enable Memory write
setmem 0xFFE00020,1,32 Remap
setmem 0xFFE00024,7,32 EBI_MCR register
setmem 0xFFE00008,0x00102002,32 CPLD config at
www.eeworm.com/read/193164/8250382
er1 mytest.er1
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
www.eeworm.com/read/293512/8288951
c mini51test.c
#include
#include
#include
#include
unsigned char xdata CPLD_WREG _at_ 0xffe4;
unsigned char xdata CPLD_RREG _at_ 0xffe5;
unsigned char xdata
www.eeworm.com/read/370520/9597849
c common.c
#include "common.h"
#define CODEC_ERROR -1
#define CODEC_OK 0
unsigned char sync_delay = 1000;
void cpld_rw_sync(int data)
{
int j=0;
sync_delay = 1000;
if(data)
for(j=0;
www.eeworm.com/read/415441/11073627
er1 jianpan.er1
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
www.eeworm.com/read/335372/12532210
er1 mcontrol.er1
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.