代码搜索：CPLD FPGA

找到约 10,000 项符合「CPLD FPGA」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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er1 tcp51.er1

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
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qmsg i2c_master_top.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/139518/13151349

er1 project.er1

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
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www.eeworm.com/read/324280/13275680

hier_info mydsp2812.hier_info

|MYDSP2812 DSP_RSTn => always1~0.IN0 DSPCLK_OUT => ~NO_FANOUT~ R_Wn => ~NO_FANOUT~ RDn => USB_CSn~0.IN0 RDn => CPLD_RDn.DATAIN WEn => DREG[7].CLK WEn => DREG[6].CLK WEn => DREG[5].CLK WEn =>
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www.eeworm.com/read/321961/13392126

c mini51test.c

#include #include #include #include unsigned char xdata CPLD_WREG _at_ 0xffe4; unsigned char xdata CPLD_RREG _at_ 0xffe5; unsigned char xdata
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www.eeworm.com/read/316203/13528469

txt prebus.txt

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
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txt 新建 文本文档.txt

注意事项： 1:目前只测试了"ARM7TDMI-S"(LPC2101-LPC2104)和"ARM7TDMI"(44B0) 2:由于CPLD的容量限制,与主机的并口通讯只支持"Multi-ICE Server"的"4-bit"模式 3:由于CPLD的容量限制,"TCK"的时钟速率为78.125KHz-10MHz(10MHz/n,n=1...128) 4:由于CPLD的
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www.eeworm.com/read/300949/13879021

er1 dk3200_1.er1

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
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www.eeworm.com/read/300949/13879309

er1 dk3200_1.er1

AHDL2BLF ABEL-HDL Processor PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
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www.eeworm.com/read/152843/5665158

h system.h

/* * linux/include/asm-arm/arch-ixp2000/system.h * * Copyright (C) 2002 Intel Corp. * Copyricht (C) 2003-2005 MontaVista Software, Inc. * * This program is free software; you can redistribute it
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