代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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www.eeworm.com/read/108632/15582785
pdf 基于fpga的嵌入式系统设计.pdf
www.eeworm.com/read/107434/15607047
doc fpga设计中关键问题的研究.doc
www.eeworm.com/read/342726/3229360
vhd test_dualport.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.test_dualport_core_pckg.all;
use work.common.all;
entity test_dualport is
port(
fpga_init_n : out std_logic; -- CPLD interface
www.eeworm.com/read/291438/8420364
qmsg traffic.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
www.eeworm.com/read/288572/8621490
c hardware.c
/*------------------------------------------------------------------------------*/
/* Project Name: Multiplexer of MPEG-II */
/* Module Name: */
/* Purpose
www.eeworm.com/read/286614/8755401
cmd_log modulator.cmd_log
xst -ise "E:/modulator/modulator_fpga/modulator/modulator" -intstyle ise -ifn modulator.xst -ofn modulator.syr
xst -ise "E:/modulator/modulator_fpga/modulator/modulator" -intstyle ise -ifn modulator.
www.eeworm.com/read/426999/8986287
qmsg top_7279.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/379154/9205815
ucf top.ucf
#####################
# clock constraints #
#####################
#
#specifying clock periods
#133 MHz
NET "sys_clk" PERIOD = 7.5ns ;
NET "fpga_clk" PERIOD = 7.5ns ;
NET "fpga_clk2x" PERIOD
www.eeworm.com/read/372667/9498674
fld ep2c5q208.fld
G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db
EP2C5Q208