代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
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cpld
--SEL_ampl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel_ampl is
port (
key: in std_logic_vector(1 downto 0);
ampl:in std_logic_vector(
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cpld
--RSNAND
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rsnand is
port(r_in:in std_logic;
s_in:in std_logic;
q_out:out std_logic);
end rsnand;
--
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cpld
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: testrom.vhd
-- Meg
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cpld
-- MAX+plus II - generated Memory Initialization File
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support informati
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cpld
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
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cpld
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: test.vhd
-- Megafu
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cpld
--addr_a_f
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr_a_f is
port(
sel: in std_logic_vector( 1 downto 0);
sel_a_f:in std_logic;
a
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cpld
testrom_inst : testrom PORT MAP(
address => address_sig,
inclock => inclock_sig,
outclock => outclock_sig,
q => q_sig
);
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity fpdpsk is
port(clock:in STD_LOGIC;
mode:in STD_LOGIC;
data:out STD_L