代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add4 is
port(cin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
package test_con is
constant N1:integer:=16;
end test_con;
use work.test_con.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ent
www.eeworm.com/read/17540/737564
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FO
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cpld
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
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cpld
--odd frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn1 is
GENERIC (N:integer:=15);
port (clk:in
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cpld
--addr_a_f
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr_a_f is
port(
sel: in std_logic_vector( 1 downto 0);
sel_a_f: in std_logic;
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cpld
-- MAX+plus II - generated Memory Initialization File
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support informati
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cpld
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: result.vh