代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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www.eeworm.com/read/17540/737551
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port (clk:in std_logic;
a,b:in std_logic_vector(15 downto 0);
q:ou
www.eeworm.com/read/17540/737552
cpld
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg4_1 is
PORT(d:in std_logic_vector(3 downto 0);
clk : IN std_logic;
q:out std_logic_vector(3 downto 0));
END reg4_1;
ARCHITEC
www.eeworm.com/read/17540/737553
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mydivider is
port(divident:in std_logic_vector(3 downto 0);
dividor:in std_logic
www.eeworm.com/read/17540/737554
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737555
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mul_8 is --接口
port(clk:in std_logic;
x:in integer range -128 to 127;
a:in std_logi
www.eeworm.com/read/17540/737556
cpld
library ieee;
use ieee.std_logic_1164.all;
entity f_adder IS
port (ain,bin,cin : IN STD_LOGIC;
cout,sum : OUT STD_LOGIC );
end entity f_adder;
architecture fd1 OF f_adder IS
www.eeworm.com/read/17540/737557
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737558
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737559
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8bit is
port(cin:in std_logic;
a,b:in std_logic_vector(7 downto 0);
s:out std_logic_vector(7 downto
www.eeworm.com/read/17540/737560
cpld
library ieee;
use ieee.std_logic_1164.all;
entity h_adder IS
PORT (a, b : IN STD_LOGIC;
co, so : OUT STD_LOGIC);
end h_adder;
architecture fh1 OF h_adder is
BEGIN
s