代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/339544/12226867
o cpld.o
www.eeworm.com/read/339544/12226884
make_cpld
/opt/host/armv4l/bin/armv4l-unknown-linux-gcc -D __KERNEL__ -I/s3c2410_linux/kernel/include -DMODULE -c -o CPLD.o CPLD.c
www.eeworm.com/read/252424/12283289
h cpld.h
#define pNAND_BaseaAddr (volatile unsigned char *)0x2c0f0000
#define NAND_CLE 0x0400
#define NAND_ALE 0x0800
#define NAND_CE 0x0200
#define NAND_RDY 0x0100
www.eeworm.com/read/232923/14177712
h cpld.h
#include "reg52.h"
#include "absacc.h"
#include
#include
#define Busy 0x80 // 忙判别位
#pragma SAVE
#pragma REGPARMS
extern unsigned char adc(unsigned char a);
extern vo
www.eeworm.com/read/232923/14177746
h cpld.h
#include "reg52.h"
#include "absacc.h"
#include
#include
#define Busy 0x80 // 忙判别位
#pragma SAVE
#pragma REGPARMS
extern unsigned char adc(unsigned char a);
extern vo
www.eeworm.com/read/229686/14325240
txt cpld.txt
cpld 与8051的总线接口VHDL源码
-------------------------------------------------------------------------------------------
关于系统的说明：
8051工作于11.0592MHZ,RAM扩展为128KB的628128,FlashR
www.eeworm.com/read/229558/14329958
h cpld.h
/*****************************************************************************/
/*function: this header file has defined the registers' addresses and register's bit defination */
/*
www.eeworm.com/read/229546/14331002
pdf cpld设计.pdf
www.eeworm.com/read/222255/14699308
pdf cpld设计.pdf
www.eeworm.com/read/222127/14703721
txt cpld.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fq_divider IS
generic(n:integer:=60000);
PORT(
CLK,reset: IN STD_LOGIC;
CLK_OUT