代码搜索：CPLD FPGA
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www.eeworm.com/read/286030/8792925
c cpld.c
/*******************************************************************************
* Copyright 2004-2005 - Software Design Solutions, Inc. All rights reserved.
*
* Portions of this work have been
www.eeworm.com/read/286030/8792934
h cpld.h
/*H***************************************************************************
*
* $Archive:: $
* $Revision: 1.1 $
* $Date: 2005/05/1
www.eeworm.com/read/283022/9046843
pdf cpld.pdf
www.eeworm.com/read/170403/9807811
h cpld.h
/*****************************************************************************/
/*function: this header file has defined the registers' addresses and register's bit defination */
/*
www.eeworm.com/read/170402/9807836
h cpld.h
/************************************************************/
/* define base addresses */
/************************************************************/
#def
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txt cpld.txt
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY unicntr IS
GENERIC(n : Positive := 8); --size of counter/shifter
PORT(clock, serinl, serinr : IN Std_logic; --se
www.eeworm.com/read/166051/10039357
h cpld.h
#include "mcf5307.h"
#define IO_BASE_ADDR 0x30400000
#define OUT_VALVE0 0x00
#define OUT_VALVE1 0x01
#define OUT_VALVE2 0x02
#define OUT_GAIN 0x03
#define OUT_PUMP 0x04
#define OUT_S
www.eeworm.com/read/360804/10078077
rar cpld.rar
www.eeworm.com/read/359131/10165015
h cpld.h
/*****************************************************************************/
/*function: this header file has defined the registers' addresses and register's bit defination */
/*
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h cpld.h
/************************************************************/
/* define base addresses */
/************************************************************/
#def