代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/339423/9895994
cpld
www.eeworm.com/read/339423/9895995
cpld
www.eeworm.com/read/252386/6943246
cpld
www.eeworm.com/read/17540/737534
cpld
#include "DataType.h"
#include "tables.h"
#include "dct.h"
#include "flash.h"
#define DEBUG
#ifdef DEBUG
#include "serial.h"
#endif
#define CIFW 352
#define CIFH 288
LINT8 cha_y[CIFW][CIFH];
www.eeworm.com/read/17540/737535
cpld
#include "DataType.h"
void ffdct(LINT8 *mcubyte, LINT32 *array)
{
LINT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7;
LINT32 tmp10, tmp11, tmp12, tmp13;
LINT32 z1, z2, z3, z4, z5, z11, z13;
www.eeworm.com/read/17540/737536
cpld
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY videocpt IS
PORT
(
cdao : out std_logic_vector(7 downto 0); -- 验证视频数据输出口
cps
www.eeworm.com/read/17540/737537
cpld
www.eeworm.com/read/17540/737538
cpld
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ram16x8 IS
PORT(address : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
csbar, oebar, webar : IN STD_LOGIC;
data : INOUT STD
www.eeworm.com/read/17540/737539
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;
ENT
www.eeworm.com/read/17540/737540
cpld
DEPTH = 256; % Memory depth and width are required %
WIDTH = 8; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX; % Enter BIN, DEC, HEX,