代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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www.eeworm.com/read/17540/737721
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
www.eeworm.com/read/17540/737722
cpld
library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
port(a,clk1,clr1:in std_logic;
b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_
www.eeworm.com/read/17540/737723
cpld
library ieee;
use ieee.std_logic_1164.all;
entity dff4 is
port(clk,clr,d:in std_logic;
q:out std_logic);
end dff4;
architecture rtl of dff4 is
begin
process(clk)
begin
if((clk'ev
www.eeworm.com/read/17540/737724
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
www.eeworm.com/read/17540/737726
cpld
说明：由于FPGA常用模块牵涉到硬件的东西少，书中内容不是按接口分类的，而且FPGA程序有烧写通用性，一个硬件板就可以实现所有功能，读者只要根据实际需要更改引脚和跳线即可。所以光盘里没有提供电路图文件。
www.eeworm.com/read/17540/737727
cpld
www.eeworm.com/read/17540/737728
cpld
www.eeworm.com/read/17540/737729
cpld
www.eeworm.com/read/17540/737730