代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/17540/737711
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737712
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pulse_sequence is
port (
res:in std_logic; --定义复位信号
in1:in std_logic; --定
www.eeworm.com/read/17540/737713
cpld
--AD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out un
www.eeworm.com/read/17540/737714
cpld
-- division1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity division1 is
port(
clk : in std_logic;
clk4 : out std_logic);
end div
www.eeworm.com/read/17540/737715
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity light is
port (start:in std_logic; --定义初始化信号,高电平有效
clk: in std_logic; -
www.eeworm.com/read/17540/737716
cpld
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg4 IS
PORT(
d:in std_logic_vector(3 downto 0);
ci: IN std_logic;
clk : IN std_logic;
q:out std_logic_vector(3 downto 0);
www.eeworm.com/read/17540/737717
cpld
library ieee;
use ieee.std_logic_1164.all;
entity reg32bit is
port(load:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end reg32bit;
archit
www.eeworm.com/read/17540/737718
cpld
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg8 IS
PORT(
d_1:in std_logic_vector(3 downto 0);
d_2:in std_logic_vector(3 downto 0);
clk: IN std_logic;
q_1:out std_logic_v
www.eeworm.com/read/17540/737719
cpld
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg4_1 is
PORT(d:in std_logic_vector(3 downto 0);
clk : IN std_logic;
q:out std_logic_vector(3 downto 0));
END reg4_1;
ARCHITEC
www.eeworm.com/read/17540/737720
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shifter IS
PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shift_left: IN STD_LOGIC;
shift_right: IN STD_LOGIC;