代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/17540/737702
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sn74ls148 is
port(i:in std_logic_vector(7 downto 0);
s:in std_logic;
ys,yex:ou
www.eeworm.com/read/17540/737703
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder8_3_1 is
port(sel:in std_logic_vector(7 downto 0);
q:out std_logic_vecto
www.eeworm.com/read/17540/737704
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder16_4 is
port(a:in std_logic_vector(15 downto 0);
z:out std_logic_vector
www.eeworm.com/read/17540/737705
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder8_3 is
port(sel:in std_logic_vector(7 downto 0);
q:out std_logic_vector(
www.eeworm.com/read/17540/737706
cpld
library ieee;
use ieee.std_logic_1164.all;
entity dds32_2 is
port( sysclk : in std_logic; -- 系统时钟
ddsout : out std_logic_vector(9 downto 0);-- DDS输出
sel
www.eeworm.com/read/17540/737707
cpld
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: dds_dds_rom.vhd
--
www.eeworm.com/read/17540/737708
cpld
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in
www.eeworm.com/read/17540/737709
cpld
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
library lpm; -- Altera LPM
use lpm.lpm_components.all;
entity dds32_1 is
www.eeworm.com/read/17540/737710
cpld
-- code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity code is
port(
datain : in unsigned(7 downto 0);
da