代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/17540/737691
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic
www.eeworm.com/read/17540/737692
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port
www.eeworm.com/read/17540/737693
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737694
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/17540/737695
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity division1 is
port(
clk : in std_logic;
clk4 : out std_logic);
end division1;
arc
www.eeworm.com/read/17540/737696
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Speaker IS
PORT ( clk1 : IN STD_LOGIC;
Tone1 : IN INTEGER RANGE 0 TO 16#7FF#;
SpkS : OUT STD_LOGIC );
END;
A
www.eeworm.com/read/17540/737697
cpld
library ieee;
use ieee.std_logic_1164.all;
entity decoder1 is
port(cin:in std_logic_vector(7 downto 0);
k1,k2:in std_logic;
enad:out std_logic;
ring:out std_logic
);
end
www.eeworm.com/read/17540/737698
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737699
cpld
library ieee;
use ieee.std_logic_1164.all;
entity tone2 is
port(
index : in integer range 0 to 15;
code : out std_logic_vector(6 downto 0);
high : out std_logic_ve
www.eeworm.com/read/17540/737700
cpld
LPM_CONSTANa_inst : LPM_CONSTANa PORT MAP(
result => result_sig
);