代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
TFF_1_inst : TFF_1 PORT MAP(
clock => clock_sig,
aclr => aclr_sig,
aset => aset_sig,
q => q_sig
);
www.eeworm.com/read/17540/737673
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
www.eeworm.com/read/17540/737674
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity divider is
port(div_in:in std_logic;
div_cnt:in unsigned(7 downto 0);
div_out:out std_logic
);
www.eeworm.com/read/17540/737675
cpld
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: fbc_rom.vhd
-- Meg
www.eeworm.com/read/17540/737676
cpld
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: DFF.vhd
-- Megafunct
www.eeworm.com/read/17540/737677
cpld
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: L1.vhd
-
www.eeworm.com/read/17540/737678
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Tone IS
PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CODE : OUT INTEGER RANGE 0 TO 15;
HIGH : OUT STD_LOGIC;
www.eeworm.com/read/17540/737680
cpld
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY fc IS
PORT
(
s_clk : IN std_logic;
a : IN unsigned(7 downto 0);
b : IN unsigned(7 downto 0);