代码搜索：CPLD FPGA
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cpld
----------------------------------------------------------------
--
-- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.
--
---------------------------------------------------
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: DFF_81.vhd
-- Megafu
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cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_sheng is
port(
clk : in std_logic;
tone : in std_logic_vector(10 downto 0);
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cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aclink3 is
PORT(
bit_clk ,key1,sdata_in: IN STD_LOGIC;
sl:buffer std_logic
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
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cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity division is
port(
div_in:in std_logic;
div_cnt:in unsigned(7 downto 0);
div_out:out std_logic);
end divi
www.eeworm.com/read/17540/737670
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS --顶层设计
PORT ( CLK12MHZ : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);