代码搜索：CPLD FPGA
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cpld
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: DFF_1.vhd
-- Megafun
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cpld
library ieee;
use ieee.std_logic_1164.all;
entity mul2wr is
port(sel:in std_logic;
in0,in1:std_logic;
dout:out std_logic
);
end mul2wr;
architecture behav of mul2wr is
begin
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cpld
DFF_1_inst : DFF_1 PORT MAP(
clock => clock_sig,
aclr => aclr_sig,
aset => aset_sig,
data => data_sig,
q => q_sig
);
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cpld
package defcon is
constant sreg_width :integer:=20;
end defcon;
use work.defcon.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
e
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cpld
DFF_81_inst : DFF_81 PORT MAP(
clock => clock_sig,
data => data_sig,
q => q_sig
);
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
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cpld
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: TFF_1.vhd
-- Megafun
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: LPM_CONST