代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/17540/737611
cpld
:10000000758170740090C000F0740090F000F09062
:10001000D000E054E0B480FA740190F000F01200D7
:100020002380E690E000E0A2E79202545C7029E0B1
:10003000A2E082E1402230E50274035403C4F521BA
:10004000A3E0540F452
www.eeworm.com/read/17540/737612
cpld
library IEEE;
use IEEE.std_logic_1164.all;
entity PDIUSB is
port(
vm : in STD_LOGIC;
vp : in STD_LOGIC;
S0 : out STD_LOGIC;
S1 : out STD_LOGIC;
S2 : out STD_LOGIC;
S3 : out STD_L
www.eeworm.com/read/17540/737613
cpld
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity usbctrl is
port(
signal sim: in STD_LOGIC; -- 仿真时为真值
signal stim: in STD_LOGIC; -- 仿真UUT
--
signal clk48: out STD_L
www.eeworm.com/read/17540/737614
cpld
#include "usb100.h"
#define SWAP(x) ((((x) & 0xFF) > 8) & 0xFF))
#define CONFIG_DESCRIPTOR_LENGTH (sizeof(USB_CONFIGURATION_DESCRIPTOR) + sizeof(USB_INTERFACE_DESCRIPTOR) +
www.eeworm.com/read/17540/737615
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff2 is
port(clk,cd,sd,d:in std_logic;
q,notq:out std_logic);
end dff2;
ar
www.eeworm.com/read/17540/737616
cpld
library ieee;
use ieee.std_logic_1164.all;
entity sn74373 is
port(D:in std_logic_vector(8 downto 1);
OEN: in std_logic;
G:in std_logic;
Q:out std_logic_vector(8 downto 1));
end s
www.eeworm.com/read/17540/737617
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff1 is
port(clk,d:in std_logic;
q:out std_logic);
end dff1;
architecture
www.eeworm.com/read/17540/737618
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_3_8 is
port(a,b,c,e1,e2,e3:in std_logic;
y:out std_logic_vector(7
www.eeworm.com/read/17540/737619
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sn7448 is
port(lt,rbi:std_logic;
datain:in std_logic_vector(3 downto 0);
rbo_b
www.eeworm.com/read/17540/737620
cpld
-- 七段锁存译码驱动器，不带小数点，如需显示小数点，则输出结果或”10000000“
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mc14495 is
port(datain:in std_logic_v