代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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www.eeworm.com/read/17540/737601
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737602
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737603
cpld
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY counter IS
PORT
( CNT_EN :in STD_LOGIC; -- 计数使能端
D :in STD_LOGIC_VECTOR(6 do
www.eeworm.com/read/17540/737604
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/17540/737605
cpld
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/17540/737606
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter_1m is
port(clk,updn,bcdwr:in std_logic;
d,e:out std_logic_vector(9 downt
www.eeworm.com/read/17540/737607
cpld
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TestUSB is
end TestUSB;
architecture Test of TestUSB is
component USB
port(
-- usb接口
vp: in STD_LOGIC;
vm: in STD_LOG
www.eeworm.com/read/17540/737608
cpld
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity CLK is
port(
clk: in STD_LOGIC; -- 48MHz输入时钟
rst: in STD_LOGIC; -- 异步复位
clko: out STD_LOGIC; -- 24MHz输出时钟
rsto: out STD_LOGIC -
www.eeworm.com/read/17540/737609
cpld
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
www.eeworm.com/read/17540/737610
cpld
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(