代码搜索：CPLD FPGA
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www.eeworm.com/read/17540/737591
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
--lut
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut is
port (addr:in std_logic_vector(5 downto 0);
outdata:out std_logic_
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737594
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division4 is
port(lin:in std_logic_vector(3 downto 0);
clock:in std_logic;
www.eeworm.com/read/17540/737595
cpld
--sanjiao 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port(
clk :in std_logic;
dout : out std_logic_vector(5 downto 0)
)
www.eeworm.com/read/17540/737596
cpld
--SEL_ampl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel_ampl is
port (
key: in std_logic_vector(1 downto 0);
ampl:in std_logic_vector(
www.eeworm.com/read/17540/737597
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
www.eeworm.com/read/17540/737598
cpld
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
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cpld
--show 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity show is
port(
indata:in std_logic_vector(11 downto 0);
l
www.eeworm.com/read/17540/737600
cpld
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
ENTITY counters IS
PORT
(
d : IN INTEGER RANGE 0 TO 255;
clk : IN BIT;
clear : IN BIT;
ld : IN BIT;