代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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www.eeworm.com/read/17540/737581
cpld
--updown (of testup)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown is
port(r_in:in std_logic;
key:in std_logic;
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cpld
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
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cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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cpld
test_inst : test PORT MAP(
address => address_sig,
inclock => inclock_sig,
outclock => outclock_sig,
q => q_sig
);
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cpld
--dirve
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity drive is
port(din:in std_logic_vector(3 downto 0);
dout:out
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cpld
--SEL2 模块
library ieee;
use ieee.std_logic_1164.all;
entity sel2 is
port(
kin1,kin2: in std_logic;
sel:in std_logic;
fout1,fout2,aout1,aout2: out std_logic
);
end sel2;
ar
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cpld
--addr (模块)正弦
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr is
port(
clk:in std_logic;
dout:out std_logic_vector(5 downto 0)
);
end ad
www.eeworm.com/read/17540/737588
cpld
--dis_sig
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity dis_sig is
port(
key:in std_logic;
selsig:out std_logic;
selout:out std_logic_vector(2 downto 0);
se
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cpld
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/17540/737590
cpld
--fangbo 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fangbo is
port(
clk :in std_logic;
dout : out std_logic
);
end fangbo;
arch