代码搜索:COMPACT

找到约 3,584 项符合「COMPACT」的源代码

代码结果 3,584
www.eeworm.com/read/177052/5333300

cs rapienumdbthread.cs

// RapiEnumDBThread.cs - Creates a background // thread to names of database volumes and names of databases // // Code from _Programming the .NET Compact Framework with C#_ // and _Programming th
www.eeworm.com/read/340703/3265625

cs rapienumdbthread.cs

// RapiEnumDBThread.cs - Creates a background // thread to names of database volumes and names of databases // // Code from _Programming the .NET Compact Framework with C#_ // and _Programming th
www.eeworm.com/read/334276/3369419

c ch01.1.2.c

// #include // using namespace std; #include /** ** read() sort() compact() write() ** **/ void read() { cout
www.eeworm.com/read/325619/3482023

cs rapienumdbthread.cs

// RapiEnumDBThread.cs - Creates a background // thread to names of database volumes and names of databases // // Code from _Programming the .NET Compact Framework with C#_ // and _Programming th
www.eeworm.com/read/276929/4160850

pbm

#------------------------------------------------------------------------------ # pbm: file(1) magic for Portable Bitmap files # # XXX - byte order? # 0 short 0x2a17 "compact bitmap" format (Poskanz
www.eeworm.com/read/436911/1840972

all-wcprops

K 25 svn:wc:ra_dav:version-url V 35 /svn/!svn/ver/373/trunk/test/cctest END test-mark-compact.cc K 25 svn:wc:ra_dav:version-url V 56 /svn/!svn/ver/329/trunk/test/cctest/test-mark-compact.cc END test-s
www.eeworm.com/read/129640/5971524

php blocks.php

www.eeworm.com/read/189192/8485957

vhd addsub.vhd

-- -- This is the adder-subtractor vhdl module. -- this code implements a simple and compact -- adder-subtractor. -- -- Input(s): a, b, subtract -- Output(s): sum -- -- include these three
www.eeworm.com/read/189192/8485959

vhd ldenaddsub.vhd

-- -- This is an adder-subtractor VHDL module. -- The module is a parallel loadable, synchronous -- set/reset, clock enabled adder-subtractor. -- this code implements a simple and compact -- add
www.eeworm.com/read/189192/8485978

v addsub.v

// // This is the adder-subtractor verilog module. // this code implements a simple and compact // adder-subtractor. // // Input(s): a, b, subtract // Output(s): sum // declare the module