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CAN Bus 的代码
can_register_asyn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_asyn
( data_in,
data_out,
we,
clk,
rst
);
parameter WIDTH = 8; // default parame
can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
can_top.vhdsim_xlate
can_top.vhdsim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_VHDL