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xst -intstyle ise -ifn __projnav/can_fifo.xst -ofn can_fifo.syr

Release 6.1i - netgen G.23 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design can_top.ngd ... Flattening design ... Flattening design completed. Specializing design ... Ad

-- Xilinx Vhdl netlist produced by netgen application (version G.23) -- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim can_top.ngd can_top_translate.vhd -- I

// synopsys translate_off `include "timescale.v" // synopsys translate_on module can_register_syn ( data_in, data_out, we, clk, rst_sync ); parameter WIDTH = 8; // default

xst -intstyle ise -ifn __projnav/can_top.xst -ofn can_top.syr xst -intstyle ise -ifn __projnav/can_top.xst -ofn can_top.syr ngdbuild -intstyle ise -dd e:\program\fpga_program\for_fpga\can\ise\canbus

Release 6.1i - netgen G.23 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design can_top.ngd ... Flattening design ... Flattening design completed. Specializing design ... Ad